By: Alex Mercer – SeaPRwire – Dense board layouts still eat weeks of engineer time. Even advanced tools leave tough manual chores. Quilter now attacks that pain directly. Their new automated BGA fanout removes a major hand-off step. Engineers no longer prep escape routing in ECAD before upload. This heads a series of 2026 updates. They push the platform deeper into complex, high-density work. The anxiety for teams centers on hand-offs. Every manual prep step risks errors and delays.
Quilter ships physics-driven AI for full PCB layout. The latest release adds automatic BGA fanout in beta. Ball grid arrays pack hundreds or thousands of connections under chips like processors and FPGAs. Designers once routed short escape paths by hand first. Quilter now handles fanout as part of candidate generation. It picks via patterns, directions, and traces based on placement, stackup, and overall routing. Support covers standard pitch, dense arrays, and irregular patterns on application processors plus high-density connectors. Routing quality improves because the system chooses the fanout itself. Earlier platform versions guessed at inputs. That worked on simple boards. Complex ones created friction. The 2026 wave replaces guesses with direct capabilities. Projects now group iterations in one spot. Most users iterate two to four times per board. Calculated impedance profiles use the customer’s stackup and Simbeor solver. Engineers override values for net classes directly. Ground net control gives explicit layer choices and region-scoped pours for multiple domains. The setup flow exposes every layer, material, and fabricator constraint upfront. New custom component proximity constraints let users set distance rules between pins and parts inside the app. Sergiy Nesterenko, founder and CEO of Quilter, put it clearly. Engineers decide how much layout to hand over. They should not re-encode data already in their files. These releases close that gap.
The changes tighten the full design loop. Upload a schematic and outline. Quilter manages placement and routing end-to-end. It returns native ECAD files with physics checks built in. Support spans Altium, KiCad, Cadence, and Xpedition. Cloud or on-premise options fit different teams. Full clearance constraint support sits in development. It will read net-class, layer-specific, and pair-specific rules straight from inputs. Blind and buried via support comes next for HDI boards. Teams gain speed without losing control. Weeks shrink to hours. The platform respects expressed intent instead of forcing rework. Engineers stay in charge. They review candidates and tweak constraints. This shifts the bottleneck from routing drudgery to higher-level decisions. Companies running dense boards see immediate relief on BGA work. Iteration groups keep history clean. Impedance tools cut verification loops. The end result points to broader adoption. Layout teams handle more complexity with fewer people. Hardware velocity increases. Quilter keeps expanding what counts as routable without human prep. Practical next step for users involves auditing recent dense designs. Identify BGA-heavy sections that ate the most time. Run one through the updated flow. Compare prep effort and final quality. Adjust proximity or ground rules based on outcomes. Small tests reveal where the new features deliver fastest wins. That data informs bigger rollout decisions. The platform evolves from helpful assistant to core layout engine. Teams that integrate these capabilities early gain clear speed advantages in competitive hardware cycles.
Author bio:Alex Mercer, long-time senior commentator for international tech publications covering enterprise software shifts and AI infrastructure trends.